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Visualizza versione completa : Via Apollo Pro e WPCREDIT, leggete x favore!!!


Trigonus
05-03-2001, 22.23.17
Qualcuno saprebbe dirmi il sgnificato dei settaggi fatti da wpcredit dal file 11060691.pcr e se vengono abilitato o no a cosa portano, + o - velocitÓ???
PCR(PCI Configration Registers) Editor / WPCREDIT for WIN32
Copyright (c) 1998 H.Oda!

[COMMENT]=author Orca
[MODEL]=Apollo Pro series
[VID]=1106:VIA
[DID]=0691:host to PCI bridge

(00)=vendor identification
(01)=vendor identification
(02)=device identification
(03)=device identification

(04:7)=address/data stepping
[04:6]=parity error response 0=disable 1=enable
(04:5)=VGA palette snoop
(04:4)=memory write/invalidate
(04:3)=special cycle monitoring
(04:2)=bus-master enable
(04:1)=memory access enable
(04:0)=i/o access enable
(05:7)=reserved
(05:6)=reserved
(05:5)=reserved
(05:4)=reserved
(05:3)=reserved
(05:2)=reserved
(05:1)=fast back-to-back
(05:0)=SERR# enable

(06:7)=fast back-to-back
(06:6)=user definable features
(06:5)=66MHz capable
(06:4)=capability list support
(06:3)=reserved
(06:2)=reserved
(06:1)=reserved
(06:0)=reserved
[07:7]=detected parity error
(07:6)=signaled system error
[07:5]=signaled master abort
[07:4]=received target abort
(07:3)=signaled target abort
(07:1..2)=DEVSEL timing 01=medium
[07:0]=data parity err .detected

(08)=revision ID 44=693A C2=694X

(09)=programming interface
(0A)=sub class code 00h=host bridge
(0B)=base class code 06h=bridge device

[0D:3..7]=latency timer (byte) guaranteed CPU time
[0D:1..2]=latency timer writeable: read @ 75:5,4
(0D:0)=latency timer always =0

(0E)=header type 00=single function device
(0F)=built-in self test 00=not supported

(10:7)=GA base address always=08
(10:6)=GA base address always=08
(10:5)=GA base address always=08
(10:4)=GA base address always=08
(10:3)=prefetchable 1=enabled
(10:1..2)=type 00=32-bit range
(10:0)=memory space indicator 0=is memory
(11)=GA base address always=00
[12:7]=GA base address
[12:6]=GA base address
[12:5]=GA base address
[12:4]=GA base address
(12:3)=GA base address always=00
(12:2)=GA base address always=00
(12:1)=GA base address always=00
(12:0)=GA base address always=00
[13]=GA base address

[2C]=subsystem vendor ID
[2D]=subsystem vendor ID
[2E]=subsystem ID
[2F]=subsystem ID

(34)=capability list pointer
(35)=capability list pointer
(36)=capability list pointer
(37)=capability list pointer

[50:7]=In-Order Queue depth 0=1-level 1=4-level
[50:6]=read-around-write 0=disable 1=enable
[50:5]=i/o write deferable 0=disable 1=enable
[50:4]=defer retry with HLOCK 0=disable 1=enable
[50:3]=CPU PCI read retry 0=disable 1=enable
[50:2]=CPU PCI read deferred 0=disable 1=enable
[50:1]=CPU DRAM read while snoop 0=disable 1=enable
[50:0]=PCI DRAM read while snoop 0=disable 1=enable

[51:7]=CPU DRAM read 0 ws 0=disable 1=enable
[51:6]=CPU DRAM write 0 ws 0=disable 1=enable
[51:5]=DRAM read request rate 0=3T 1=2T
[51:4]=reserved
[51:3]=reserved
[51:2]=CPU DRAM prefetch depth 0=1-level 1=4-level
[51:1]=CPU DRAM post-write depth 0=1-level 1=4-level
[51:0]=concurrent CPU/PCI-master 0=disable 1=enable

[52:7]=GTL i/o buffer pull-up 0=disable 1=enable
[52:6]=reserved
[52:5]=reserved
[52:0..4]=snoop stall count 00=disable dynamic count

[53]=unknown

[58:5..7]=DRAM bank 0/1 map type
[58:4]=DRAM bank 0/1 VCM enable 0=disable 1=enable
[58:1..3]=DRAM bank 2/3 map type
[58:0]=DRAM bank 2/3 VCM enable 0=disable 1=enable
[59:5..7]=DRAM bank 4/5 map type
[59:4]=DRAM bank 4/5 VCM enable 0=disable 1=enable
[59:1..3]=DRAM bank 6/7 map type
[59:0]=DRAM bank 6/7 VCM enable 0=disable 1=enable

[56]=DRAM bank 6 end address
[57]=DRAM bank 7 end address
[5A]=DRAM bank 0 end address
[5B]=DRAM bank 1 end address
[5C]=DRAM bank 2 end address
[5D]=DRAM bank 3 end address
[5E]=DRAM bank 4 end address
[5F]=DRAM bank 5 end address

[60:6..7]=DRAM bank 6/7 type 00=FP 01=EDO 10=DDR 11=SD
[60:4..5]=DRAM bank 4/5 type 00=FP 01=EDO 10=DDR 11=SD
[60:2..3]=DRAM bank 2/3 type 00=FP 01=EDO 10=DDR 11=SD
[60:0..1]=DRAM bank 0/1 type 00=FP 01=EDO 10=DDR 11=SD

[61:6..7]=shadow CC000-CFFFF 00=none 01=w 10=r 11=rw
[61:4..5]=shadow C8000-CBFFF 00=none 01=w 10=r 11=rw
[61:2..3]=shadow C4000-C7FFF 00=none 01=w 10=r 11=rw
[61:0..1]=shadow C0000-C3FFF 00=none 01=w 10=r 11=rw
[62:6..7]=shadow DC000-DFFFF 00=none 01=w 10=r 11=rw
[62:4..5]=shadow D8000-DBFFF 00=none 01=w 10=r 11=rw
[62:2..3]=shadow D4000-D7FFF 00=none 01=w 10=r 11=rw
[62:0..1]=shadow D0000-D3FFF 00=none 01=w 10=r 11=rw
[63:6..7]=shadow E0000-EFFFF 00=none 01=w 10=r 11=rw
[63:4..5]=shadow F0000-FFFFF 00=none 01=w 10=r 11=rw
[63:2..3]=memory hole 00=none
[63:0..1]=SMI mapping

[64:7]=0/1 precharge to active 0=2T 1=3T
[64:6]=0/1 active to precharge 0=5T 1=6T
[64:4..5]=0/1 CAS latency 00=1T 01=2T 10=3T
[64:3]=0/1 DDR write enable 0=disable 1-enable
[64:2]=0/1 ACTIVE to CMD 0=2T 1=3T
[64:0..1]=0/1 bank interleave 00=none 01=2-way 10=4-way
[65:7]=2/3 precharge to active 0=2T 1=3T
[65:6]=2/3 active to precharge 0=5T 1=6T
[65:4..5]=2/3 CAS latency 00=1T 01=2T 10=3T
[65:3]=2/3 DDR write enable 0=disable 1-enable
[65:2]=2/3 ACTIVE to CMD 0=2T 1=3T
[65:0..1]=2/3 bank interleave 00=none 01=2-way 10=4-way
[66:7]=4/5 precharge to active 0=2T 1=3T
[66:6]=4/5 active to precharge 0=5T 1=6T
[66:4..5]=4/5 CAS latency 00=1T 01=2T 10=3T
[66:3]=4/5 DDR write enable 0=disable 1-enable
[66:2]=4/5 ACTIVE to CMD 0=2T 1=3T
[66:0..1]=4/5 bank interleave 00=none 01=2-way 10=4-way
[67:7]=6/7 precharge to active 0=2T 1=3T
[67:6]=6/7 active to precharge 0=5T 1=6T
[67:4..5]=6/7 CAS latency 00=1T 01=2T 10=3T
[67:3]=6/7 DDR write enable 0=disable 1-enable
[67:2]=6/7 ACTIVE to CMD 0=2T 1=3T
[67:0..1]=6/7 bank interleave 00=none 01=2-way 10=4-way

[68:7]=SDRAM open page control 0=precharge while FP/EDO
[68:6]=bank active page control 0=same bank 1=any bank
[68:5]=EDO pipeline burst 0=x222-2-222 1=x222-3-222
[68:4]=reserved
[68:3]=EDO test mode 0=disable 1=enable
[68:2]=burst refresh 0=disable 1=enable
(68:0..1)=AGP divider 00=1x 01=2/3x ?11=1/2x

(69:7)=DRAM frequency ???
(69:6)=DRAM frequency ???
[69:5]=unknown
[69:4]=unknown
[69:3]=unknown
[69:2]=reserved
[69:1]=reserved
[69:0]=reserved

[6A]=refresh counter 00=DRAM refresh disabled

[6B:6..7]=arbitration parking 00=last 01=CPU 10=AGP
[6B:5]=unknown
[6B:4]=reserved
[6B:1..3]=suspend refresh rate 00=refresh disable
[6B:0]=multi-page open 0=disable 1=enable

[6C:7]=reserved
[6C:6]=DRAM start cycle 0=with cache hit 1=after
[6C:5]=MD-to-HD pop 0=normal 1=add 1T
[6C:4]=DDR W-to-R turnaround 0=1T 1=2T
[6C:3]=fast single-cycle 0=disable 1=enable
[6C:0..2]=SDRAM mode select 00=normal

[6D:7]=MAB output 0=disable 1=enable
[6D:5..6]=delay DRAM read latch 00=disable
[6D:4]=MD drive 0=8mA 1=6mA
[6D:3]=SDRAM command drive 0=16mA 1=24mA
[6D:2]=MA[2-13] drive 0=16mA 1=34mA
[6D:1]=CAS drive 0=8mA 1=12mA
[6D:0]=RAS drive 0=16mA 1=24mA

[6E:7]=ECC/EC mode 0=EC 1=ECC
[6E:6]=reserved
[6E:5]=SERR on multi-bit error 0=disable 1=enable
[6E:4]=SERR on single-bit error 0=disable 1=enable
[6E:3]=bank 6/7 ECC/EC enable ? 0=disable 1=enable
[6E:2]=bank 4/5 ECC/EC enable 0=disable 1=enable
[6E:1]=bank 2/3 ECC/EC enable 0=disable 1=enable
[6E:0]=bank 0/1 ECC/EC enable 0=disable 1=enable

[6F:7]=multi-bit error detected
[6F:4..6]=multi-bit error bank
[6F:3]=single-bit error detectd
[6F:0..2]=single-bit error bank

[70:7]=CPU to PCI post-write 0=disable 1=enable
[70:6]=PCI to DRAM post-write 0=disable 1=enable
[70:5]=reserved
[70:4]=PCI to DRAM prefetch 0=disable 1=enable
[70:3]=CPU/PCI buffer fast cycle 0=disable 1=enable
[70:2]=PCI-master read caching 0=disable 1=enable
[70:1]=delayed transaction 0=disable 1=enable
[70:0]=slave-idle fast cycle 0=disable 1=enable

[71:7]=dynamic burst 0=disable 1=enable
[71:6]=byte merge 0=disable 1=enable
[71:5]=reserved
[71:4]=PCI i/o post-write 0=disable 1=enable
[71:3]=PCI burst 0=disable 1=enable
[71:2]=PCI fast back-to-back W 0=disable 1=enable
[71:1]=quick Frame generation 0=disable 1=enable
[71:0]=1ws PCI cycles 0=disable 1=enable

[72:7]=retry status 1=reties over limit
[72:6]=retry timeout action 0=don't stop 1=normal
[72:4..5]=retry limit 00=2 01=4 10=16 11=64
[72:3]=clear & continue retry 0=disable 1=enable
[72:2]=CPU backoff on PCI retry 0=disable 1=enable
[72:1]=reduce 1T for FRAME gen. 0=disable 1=enable
[72:0]=reserved

[73:7]=reserved
[73:6]=PCI-master 1ws write 0=0ws 1=1ws
[73:5]=PCI-master 1ws read 0=0ws 1=1ws
[73:4]=reserved
[73:3]=PCI-m. write timeout STOP 0=disable 1=enable
[73:2]=PCI-m. read timeout STOP 0=disable 1=enable
[73:1]=LOCK function 0=disable 1=enable
[73:0]=PCI broken timer enable 0=disable 1=enable

[74:7]=PCI-m. read enh. prefetch 0=disable 1=enable
[74:6]=PCI-master write merge 0=disable 1=enable
[74:5]=reserved
[74:4]=unknown
[74:3]=unknown
[74:2]=unknown
[74:1]=unknown
[74:0]=reserved

[75:7]=arbitration mechanism 0=PCI priority 1=CPU/PCI
[75:6]=arbitration mode 0=REQ-based 1=FRAME-based
(75:4..5)=latency timer shows reg 0D:1,2
[75:0..3]=PCI-master bus timeout 00=disable xx=x32 clks

[76:7]=AGP-PCI retry disconnect 0=disable 1=enable
[76:6]=CPU latency timer bit0 1=CPU has no time slot
[76:4..5]=priority rotation control 00=disabled
[76:3]=reserved
[76:2]=reserved
[76:1]=reserved
[76:0]=reserved

[77:6..7]=reserved
[77:0..5]=chip test mode do not use !!!

[78:7]=i/o port 22 access 0=PCI 1=internal
[78:6]=suspend refresh type 0=CBR 1=self-refresh
[78:5]=normal refresh 0=use HCLK 1=use SUSCLK
[78:4]=dynamic clock control 0=disable 1=enable
[78:3]=GCKRUN de-assertion 0=disable 1=enable
[78:2]=reserved
[78:1]=PCKRUN/GCKRUN pin control 0=disable 1=enable
[78:0]=CKE pins function 0=disable 1=enable

[79]=unknown

[7A]=unknown

[7B]=unknown

[7E:6..7]=reserved
[7E:0..5]=DLL test mode do not use !!!

[7F]=DLL test mode do not use !!!

[80:7]=flush page TLB 0=disable 1=enable
[80:6]=reserved
[80:5]=reserved
[80:4]=reserved
[80:3]=PCI#1 master GA access 0=disable 1=enable
[80:2]=PCI#2 master GA access 0=disable 1=enable
[80:1]=CPU GA access 0=disable 1=enable
[80:0]=AGP GA access 0=disable 1=enable
(81)=reserved test mode status
(82)=reserved
[83]=reserved

[84]=AGP aperture size

[88:7]=reserved
[88:6]=reserved
[88:5]=reserved
[88:4]=reserved
[88:3]=reserved
[88:2]=PCI-m. GA direct access 0=disable 1=enable
[88:1]=gaphics aperture enable 0=disable 1=enable
[88:0]=GART non-cachable 0=cache 1=non-cache
[89:4..7]=GART base address adress=8B:8A:89
[89:3]=reserved
[89:2]=reserved
[89:1]=reserved
[89:0]=reserved
[8A]=GART base address
[8B]=GART base address

[8C]=unknown

(A0)=AGP ID 02=AGP
(A1)=pointer to next list
(A2:4..7)=major revision
(A2:0..3)=minor revision
(A3)=reserved

(A4:7)=reserved
(A4:6)=reserved
(A4:5)=more then 4GB support
(A4:4)=Fast Writes support
(A4:3)=reserved
(A4:2)=4x rate support
(A4:1)=2x rate support
(A4:0)=1x rate support
(A5:7)=reserved
(A5:6)=reserved
(A5:5)=reserved
(A5:4)=reserved
(A5:3)=reserved
(A5:2)=reserved
(A5:1)=Side Band Address support
(A5:0)=reserved
(A6:7)=reserved
(A6:6)=reserved
(A6:5)=reserved
(A6:4)=reserved
(A6:3)=reserved
(A6:2)=reserved
(A6:1)=reserved
(A6:0)=reserved
(A7)=maximum AGP requests xx=max. number -1

[A8:7]=reserved
[A8:6]=reserved
[A8:5]=reserved
[A8:4]=Fast Write enable 0=disable 1=enable
[A8:3]=reserved
[A8:2]=4x mode enable 0=disable 1=enable
[A8:1]=2x mode enable 0=disable 1=enable
[A8:0]=1x mode enable 0=disable 1=enable
[A9:7]=reserved
[A9:6]=reserved
[A9:5]=reserved
[A9:4]=reserved
[A9:3]=reserved
[A9:2]=reserved
[A9:1]=Side Band Address enable 0=disable 1=enable
[A9:0]=AGP enable 0=disable 1=enable
[AA:7]=reserved
[AA:6]=reserved
[AA:5]=reserved
[AA:4]=reserved
[AA:3]=reserved
[AA:2]=reserved
[AA:1]=reserved
[AA:0]=reserved
[AB]=request depth

[AC:7]=reserved
[AC:6]=reserved
[AC:5]=reserved
[AC:4]=reserved
[AC:3]=2x rate support read as A4:1
[AC:2]=Force Fence 0=disable 1=enable
[AC:1]=AGP arbitation parking 0=disable 1=enable
[AC:0]=AGP arbitation priority 0=CPU 1=PCI master

[B0]=unknown
[B1]=unknown
[B2]=unknown

(C0)=capability ID ID=???
(C1)=pointer to next list
(C2:4..7)=major revision
(C2:0..3)=minor revision
(C3)=reserved

[F0]=BIOS scatch pad (no function)
[F1]=BIOS scatch pad (no function)
[F2]=BIOS scatch pad (no function)
[F3]=BIOS scatch pad (no function)
[F4]=BIOS scatch pad (no function)
[F5]=BIOS scatch pad (no function)
[F6]=BIOS scatch pad (no function)
[F7]=BIOS scatch pad (no function)

[FC:7]=reserved
[FC:6]=reserved
[FC:5]=reserved
[FC:4]=reserved
[FC:3]=reserved
[FC:2]=reserved
[FC:1]=reserved
[FC:0]=reserved do not use !!!
[FD]=reserved

[FE]=reserved
[FF]=reserved
Ecco fatto, ciao!